Thin Film Deposition

Process Development

ARC deposits thin films by Sputtering, Evaporation, Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). Each of these methods offer a project designer a variety of process design options.

ARC has over 60 Sputtering targets in house as listed in the Target Chart below. These targets fall into four categories: Elementals, Dielectrics/Glasses, Magnetic Alloys and Other Alloys.  Custom Sputtering target compositions of any of these categories are available through ARC’s qualified suppliers.

ARC has 9 Sputtering tools in the Micro-Nano Fab, several are multiple target tools and several are load lock tools.

Evaporation Deposition is used for Indium which is the deposition solder of choice for Hybridization customers when bonding two dissimilar substrates such as in a Focal Plane Arrays (compound Semiconductor) – Read Out IC’s (Silicon) process. Evaporation deposition provides thick films needed for the Bumping process.

Sputter Tools - ARC has over 60 target materials (see below)

CVD and ALD are also available. Chemical Vapor Deposition is an excellent technique when conformal coating a structure is required. Sputtering is a line-of-sight deposition process and will not uniformly coat complex topological features on a wafer. ALD is the process of choice when an ultra-thin but very uniform coating is required.

Front Side – Back Side Patterning

Photolithographic Patterning is the process whereby a wafer is coated with photoresist in a photoresist Spinner, Figure 1 (right), the spinning creates a uniform thin coat of photoresist. The wafer is then placed in the MA6 Mask Aligner, Figure 2 (right) which has a typical Mask, Figure 3 (below) inserted. The wafer is then exposed and the Mask pattern, Figure 4 (below) is transferred to the wafer. The MA6 is capable of both front-side and back side patterning while keeping both patterns aligned to each other. ARC offers a Class 100 clean room for this process.

Also available are a Canon Stepper and Heidelberg Direct Write system when a project requires these tools.

Photoresist Spinners
Figure 1. Photoresist Spinners
Figure 2. Karl Suss MA6 Front Side/Back Side Aligner Mask Aligner

Shown right is the actual mask glass plate, the CAD mask pattern drawing (GDS2 format), Figure 4, and the final Waveguide plated Copper with plated though holes which couples the backside to the frontside. The pattern has been aligned to the pre-drilled holes using fiducials on the wafer.

Figure 3. Mask for the Waveguides shown right
Waveguide CAD Pattern
Figure 4. Waveguide CAD Pattern
40GHz Waveguides on Aluminum Oxide with Laser Drilled Holes
Figure 5. 40GHz Waveguides on Aluminum Oxide with Laser Drilled Holes

Indium Bumping

ARC has developed the skill to offer our customers to high resolution Indium “bumped” wafers for Hybridizing two wafers as mentioned above. Shown right in Figure 6 is a portion of a wafer showing the bump placement relative to the gold pads. On the far right in Figure 7, is a wider section of the Infrared Focal Plane Array (IrFPA) wafer and/or the Read Out Integrated Circuit (ROIC). Currently IrFPA/ROIC devices may have 1K x 1K pixels which means connecting 1 million pixels.

5μm bumps on a 12μm pitch
Figure 6. 5μm bumps on a 12μm pitch
High Definition Bump Array
Figure 7. High Definition Bump Array


The three primary methods for Dry Etching are Ion Milling, for thin films shown in Figure 8 (right); Reactive Ion Etch (RIE) for somewhat thicker films; and Deep RIE for very thick structures, Figure 9 (right).

1μm particles defined using Ion Milling
Figure 8. 1μm particles defined using Ion Milling
Figure 9. Plate curvature needed to identify ions with various mass and charge were fabricated using RIE

Wet Etching is a wafer processing technique that is ideal for certain materials, e.g. silicon where a known etchant exists. Careful masking and control of the etchant are required in order to achieve the desired features.

ARC is skilled in using both Dry Etch and Wet Etch techniques on behalf of customer projects.

Backside Metallization

In creating devices where a wafer has devices on the front side and where connecting electrically to the backside of a wafer is a requirement, such as providing a means of grounding, a conducting material such as gold (Au) is sputtered over the back surface.

Gold deposited on entire 8" silicon wafer
Figure 10. Gold deposited on entire 8" silicon wafer

Hydrogen Annealing

Film annealing is required when modifying a material’s as-sputtered grain structure in order to achieve a certain grain structure with more satisfactory performance parameters. ARC has the appropriate Annealing ovens and the processes to accomplish the task.

Annealing Oven Chamber
Figure 11. Annealing Oven Chamber

Passivation – Boron Hydride

Boron Hydride is deposited by CVD. Shown left is the ARC Boron Hydride deposition chamber – Boron hydride is often selected for its corrosion resistance properties and its resistance to high temperatures.

Passivation – Parylene

Parylene is deposited by CVD. Shown left is the Parylene deposition chamber – Parylene is the common name for poly(p-xylylene) and is often used for corrosion protection on top of a thin film deposited on Beryllium.

Use of high temperature polymers, such as a polyimide for the polymer layer, can allow the x-ray window or layers to withstand high temperatures. Use of sufficiently thick layers of materials can allow the window or layers to withstand a differential pressure of at least 1 atmosphere improved gas impenetrability, improved corrosion resistance, and improved ability to withstand higher temperatures

For more information on your specific project contact Steve Ellison at 651-789-9011, ARC’s Micro Fabrication Manager or send us an email through our contact page.