Wafer Back End

Wafer Back End of Line (BEOL) best describes those fabrication processes which take place after a semiconductor wafer has been processed and is ready for the additional processing usually beyond the environment of the ultra-clean cleanroom.  Wafer types include CMOS, Compound Semiconductor and MEMS device wafers to name a few.  ARC is a natural and competent partner for those customers who need these services since ARC fabricates its own MEMS devices, has years of experience processing thin film devices and has developed skills in moving wafers between precision machining and its micro-nano fab. 

ARC processes wafers up to 8” in diameter and has also developed a process for handling diced quarter sections of 8” wafers. During the prototype phase and up to early limited production this is a preferred wafer handling typography due to the number of die needed for a project where a wafer fab had more than one project on a wafer to cut cost.

Customers may elect to avail themselves of any of the services below that fit their project needs.

• Wafer Thinning
• Backside Metallization

• Lapping & Polishing
• Photolithographic Patterning
• Testing

• Hydrogen Annealing
• Dicing
• Packaging/Hybridization

• Bare Die Picking
• Wire Bonding

Projects often require a unique set of processes in order to achieve a customer’s end goal. ARC has developed the throughput capability to integrate a process flow for each BEOL project.

Drawings and sketches may be submitted via our contact page. You will be contacted shortly to discuss your project.

Wafer Thinning

Figure 1. A Wafer thining process is illustrated in the above picture, wafer sizes up to 8

Lapping & Polishing

Figure 2. ARC’s Lapping Tool set in addition to CMP and standard lappers also include electronic lapping guide capability

Backside Metallization

Figure 3. A six inch wafer is shown with backside gold metallization, other metals are available as well

Photolithographic Patterning

Figure 4. Karl Suss MA/BA 6 Mask Aligner for Front-side/Backside Patterning in Class 100 Cleanroom. CAD mask design is done at ARC

Photoresist Spinners

Figure 5. Photoresist Spinners apply thin uniform coatings of photoresist.

Patterned Wafer

Figure 6. Patterned 6” wafer after ARC mask design has been completed and customer verification has been received

Typical Patterned Device

Figure 7. Patterned Die for a 0.5 mm Anisotropic Magnetoresistance (AMR) Dual Barber Pole Sensor

Hydrogen Annealing

Figure 8. ARC’s Hydrogen Annealing Furnace for those customers that require

Precision Dicing

Figure 9. Dicing tools mounted on air suspension tables to reduce external vibration for better dicing precision

Bare Die & Wafer Inspection

Figure 10. Automated die/wafer inspection informs the die “picker” as to which die should be excluded

Bare Die Picking

Figure 11. Die can be “picked” from the dicing media and placed on surface mount tape for pick and place tools or placed in die trays

Wire Bonding

Figure 12. Extreme wire bonding is shown for high current draw situations such as for laser diodes


Figure 13. Die mounted in a carrier, wire bonded and epoxy under filled for stability


Figure 14. ARC probe testing of Focal Plane Arrays – ROIC assembly